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Alba Iulia
Thursday, June 4, 2020

Watch out, ARM? New 64-bit Synopsys ARC cores triple performance

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Few people know that the ARC processor architecture is one of the most common architectures along with ARM, MIPS, and x86. Developed in the 1980s, the ARC architecture is used in various controllers for a wide range of high-tech products, and each year around ARC is produced 1.5 billion devices.

The other day, Synopsys Corporation announced a new generation of 32- and 64-bit ARC processor cores, which promise to increase productivity compared to their predecessors by three times, and will also allow building systems-on-a-chip with 12 cores. Thus, the new cores will allow Synopsys to compete with ARM in a number of new directions.

“Embedded applications like controllers for solid state drives or network equipment are becoming more complex, which requires a significant increase in performance with limited power consumption and form factors.” Said John Koeter, senior vice president of marketing and intellectual property strategy at Synopsys. “With the release of the new ARCv3 architecture and ARC HS5x and HS6x cores, developers will be able to meet the growing performance requirements of their SoC today and in the future. ”

Synopsys Logo

New Synopsys DesignWare ARC processor families include 32-bit cores HS56 / HS57D / HS58 and 64-bit kernels HS66 / HS68. Freshly announced processors are designed for a wide range of applications, such as solid state drive controllers (SSDs), network controllers, autopilots for vehicles, infotainment systems for cars, and many others. Taking into account the growing demands on the amount of RAM, 64-bit ARC HD6x will allow you to create systems with 4.5 Pbytes of DRAM, while devices based on ARC HD5x will have to be limited to smaller volumes. However, the actual amount of supported RAM will most likely be dictated by the operating system used, and the visible benefits of 64-bit CPUs will be dictated by a wider pipeline and a large register file.

As for the DesignWare ARC HS5x and DesignWare ARC HS6x architectures, they support the ARCv3 instruction set, which can be extended with APEX (ARC Processor EXtensions) instructions if one of the clients needs something specific. In addition, the ARC HS57D features an ARCv3DSP digital signal processor with support for 150 teams. The new cores have a conveyor depth of 10 steps, can execute two instructions per cycle, and are equipped with a 128-bit floating-point operation module. At the same time, the most advanced versions of the cores support the second level cache (L2) up to 16 MB in size.

Block diagram of the Synopsys DesignWare ARC HS5x and DesignWare ARC HS6x processors

Block diagram of the Synopsys DesignWare ARC HS5x and DesignWare ARC HS6x processors

In terms of performance, Synopsys claims 3 DMIPS per MHz in integer calculations, as well as 5.1 CoreMark per MHz, which is very good for tiny cores with minimal power consumption. So, 3 DMIPS per MHz is higher than that of fairly powerful processors Cortex-a55, while 5.1 CoreMark at MHz is higher than any ARM processor for microcontrollers.

Synopsys DesignWare ARC HS5x and HS6x processor cores

HS5x HS6x
HS56 HS57D HS58 HS66 HS68
Instruction set ARCv3
APEX Instructions Are supported
Capacity 32-bit 64-bit
Instructions per beat 2
Conveyor length 10 steps
DSP ARCv3DSP
150 instructions
FPU accuracy FP16, FP32, FP64
Processor cluster 12 cores
Accelerators per cluster 16 boosters
L1 Instruction cache + Data cache
L2 16 MB 16 MB
Maximum memory capacity 64 GB (OS dependent) 4.5 petabytes
Frequency (at t / n 16FFC) 1.8 GHz
Dmips 5400 DMIPS per core / 3 DMIPS per MHz
Coremark 9180 CoreMark per core / 5.1 CoreMark per MHz

One of the key features of the new DesignWare ARC HS5x and DesignWare ARC HS6x family is the ability to create system-on-chip (system-on-chip, SoC) systems with 12 general-purpose processor cores and 16 specialized accelerators. Each core / accelerator in such a processor operates at its own clock frequency and uses its own power subsystem to maximize energy efficiency. Along with the new cores, Synopsys also offers an in-processor cache-coherent connection with a data transfer rate of 800 GB / s.

This kind of SoC based on the ARC architecture is not very common today, but taking into account promising processors for autopilot systems, data storage, data flow control, multi-core and various accelerators will come in handy. The latter will enable Synopsys to compete with ARM cores for a place in the SoC for these applications, which has not happened so far. So, DesignWare ARC HS5x and DesignWare ARC HS6x cores are already interested in the manufacturer of solid-state drives Starblaze.

“Developers of high-performance embedded solutions are constantly confronted with new challenges in achieving high performance when using large amounts of memory and limitations in energy consumption and size.” – said Bruce Cheng (Bruce Cheng), a senior fellow at Starblaze. “Synopsys’s new 32-bit ARC HS5x processors and 64-bit HS6x multi-core processors will enable us to move to a new level of energy efficiency that is not offered by other processors currently on the market.”

Synopsys Revenue Growth

Synopsys Revenue Growth

Synopsys will begin offering ARC cores HS56, HS57D, HS58, HS66, HS68, as well as their multiprocessor versions HS56MP, HS57DMP, HS58MP, HS66MP, HS68MP, starting in the third quarter of 2020. In addition, the company will offer the ARC MetaWare Development Toolkit package for creating microcircuits based on these cores, as well as a simulator and verifier for checking the SoC functionality before being implemented in silicon. As for support from operating systems, the new kernels will be compatible with a number of Linux, Zephyr distributions, as well as various kinds of proprietary operating systems.

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